GPUOcelot

Class List

Here are the classes, structs, unions and interfaces with brief descriptions:
__cudaFatCubinEntry
__cudaFatCudaBinary2EntryRec
__cudaFatCudaBinary2HeaderRec
__cudaFatCudaBinaryRec
__cudaFatCudaBinaryRec2
__cudaFatDebugEntryRec
__cudaFatElfEntryRec
__cudaFatPtxEntry
__cudaFatSymbol
__exception
__fsid_t
__locale_struct
__mbstate_t
__pthread_internal_list
pthread_mutex_t::__pthread_mutex_s
__sigset_t
_G_fpos64_t
_G_fpos_t
_IO_cookie_io_functions_t
_IO_FILE
_IO_marker
trace::MemoryChecker::AllocationA class for a cached memory allocation
analysis::AnalysisAn analysis that can be constructed for aiding IR transforms
util::ExtractedDeviceState::Application
transforms::AssignFallThroughEdge
executive::ATIExecutableKernel
executive::ATIGPUDeviceATI GPU Device
ir::BasicBlockA basic block contains a series of instructions terminated by control flow
transforms::BasicBlockPassA pass over a single basic block in a kernel
analysis::DataflowGraph::BlockA class for referring to a generic basic block of instructions
analysis::ProgramStructureGraph::Block
analysis::ProgramStructureGraph::Block::block_iteratorAn iterator over basic blocks
analysis::ControlTree::BlockNodeA sequence of nodes
ir::BlockSetCompare
analysis::DataflowGraph::BlockVector_Hash
analysis::BranchInfo
CALdeviceattribsRec
CALdeviceinfoRec
CALdevicestatusRec
CALdomain3DRec
CALdomainRec
cal::CalDriverProvides access to the CAL runtime/driver
CALfuncInfoRec
CALprogramGridArrayRec
CALprogramGridRec
char1
char3
api::OcelotConfiguration::Checkpoint
executive::RemoteDevice::ConnectionManagerA singleton to manage communication
analysis::ProgramStructureGraph::Block::const_block_iteratorA const iterator over basic blocks
analysis::ProgramStructureGraph::Block::const_iteratorA const iterator
analysis::ProgramStructureGraph::Block::const_predecessor_iteratorA const iterator over block predecessors
analysis::ProgramStructureGraph::Block::const_successor_iteratorAn iterator over block successors
cuda::CudaDriverFrontend::ContextCUDA Driver API context
ir::ControlFlowGraph
analysis::ControlTreeComputes the Control Tree as defined in Muchnick's textbook
transforms::ConvertPredicationToSelectPassA class for a pass that converts all predicate instructions to conditional select
executive::CooperativeThreadArray
executive::CTABarrier
executive::CTAContext
CUDA_ARRAY3D_DESCRIPTOR_st
CUDA_ARRAY_DESCRIPTOR_st
CUDA_MEMCPY2D_st
CUDA_MEMCPY3D_st
cudaChannelFormatDesc
cudaDeviceProp
cuda::CudaDriverDynamic interface to the cuda driver
cuda::CudaDriverFrontendImplements the CUDA Driver API front-end to GPU Ocelot
CudaDriverFrontendDestructor
cuda::CudaDriverInterfaceDynamic interface to the cuda driver
cudaExtent
cudaFuncAttributes
cudaIpcEventHandle_st
cudaIpcMemHandle_st
cudaMemcpy3DParms
cudaMemcpy3DPeerParms
cudaPitchedPtr
cudaPointerAttributes
cudaPos
cuda::CudaRuntime
api::OcelotConfiguration::CudaRuntimeImplementation
cuda::CudaRuntimeInterface
cuda::CudaWorkerThreadA worker thread that allows asynchronous execution of kernels on an Ocelot device
CUdevprop_st
CUuuid_st
ir::PTXStatement::Data
executive::LLVMModuleManager::DatabaseMessage
analysis::DataflowGraphA class representing a graph of block of instructions, showing which registers are alive in each basic block
transforms::DeadCodeEliminationPassA transform to perform dead code elimination on a PTX kernel
api::OcelotConfiguration::TraceGeneration::DebuggerConfiguration properties for trace::InteractiveDebugger
transforms::DefaultLayoutPassConstruct an instruction vector without reconverge points
analysis::DefaultProgramStructureImplements a naive mapping over existing basic blocks
executive::Device
ir::Dim3
dim3
cuda::Dimension
executive::LLVMContext::DimensionA 3-D dimension corresponding to the CUDA notion
analysis::DirectionalGraph
div_t
analysis::DivergenceAnalysisDivergenceAnalysis implements divergence analysis. The divergence analysis goes over the program dataflow graph and finds all the variables that will always hold the same values for every thread
analysis::DivergenceGraph
analysis::DominatorTree
ir::BasicBlock::DotFormatterObject that formats the string representation of a basic block used in the DOT output of the graph
test::Double
double1
double3
drand48_data
ir::BasicBlock::EdgeAn edge connects two basic blocks
executive::EmulatedKernel
executive::EmulatorCallStackA class implementing a multi-threaded variably sized call stack for the emulator device
executive::EmulatorDevice
parser::PTXParser::Exception
translator::Translator::ExceptionAn exception for distinguishing between exceptions
executive::ExecutableKernel
api::OcelotConfiguration::Executive
ir::ExternalFunctionSet::ExternalFunction
ir::ExternalFunctionSetHolds a collection of external functions
executive::ExternalKernelDefines a method in which kernel implementations may be overridden by externally specified kernels
util::ExtractedDeviceState
transforms::SubkernelFormationPass::ExtractKernelsPass
cuda::FatBinaryContextClass allowing sharing of a fat binary among threads
fd_set
float1
float3
parser::PTXParser::State::FunctionPrototype
executive::LLVMModuleManager::GetFunctionMessage
ir::GlobalA class for referencing preinitialized global variables
util::ExtractedDeviceState::GlobalAllocation
std::hash< analysis::ControlTree::NodeList::const_iterator >
std::hash< analysis::ControlTree::NodeList::iterator >
std::hash< analysis::DataflowGraph::iterator >
std::hash< analysis::DataflowGraph::Register >
std::hash< analysis::DataflowGraph::RegisterPointer >
std::hash< ir::ControlFlowGraph::const_iterator >
std::hash< ir::ControlFlowGraph::InstructionList::const_iterator >
std::hash< ir::ControlFlowGraph::InstructionList::iterator >
std::hash< ir::ControlFlowGraph::iterator >
std::hash< ir::PTXOperand::DataType >
remote::RemoteDeviceMessage::Header
HexTo< ElemT >
cuda::HostThreadContext
analysis::ControlTree::IfThenNodeIf-Then node
ir::ILAbs
ir::ILAdd
ir::ILAnd
ir::ILBinaryInstructionA generic 2 operand instruction
ir::ILBreak
ir::ILCmov_Logical
ir::ILCos_Vec
ir::ILDiv
ir::ILElse
ir::ILEnd
ir::ILEndIf
ir::ILEndLoop
ir::ILEq
ir::ILExp_Vec
ir::ILFence
ir::ILFfb_Hi
ir::ILFma
ir::ILFtoI
ir::ILFtoU
ir::ILGe
ir::ILIadd
ir::ILIand
ir::ILIeq
ir::ILIfLogicalNZ
ir::ILIfLogicalZ
ir::ILIge
ir::ILIlt
ir::ILImax
ir::ILImin
ir::ILImul
ir::ILIne
ir::ILInegate
ir::ILInot
ir::ILInstructionA class used to represent any IL Instruction
ir::ILIor
ir::ILIshl
ir::ILIshr
ir::ILItoF
ir::ILIxor
ir::ILKernelA class containing a complete representation of an IL kernel
ir::ILLds_And_Resource
ir::ILLds_Load_Id
ir::ILLds_Or_Resource
ir::ILLds_Read_Add_Resource
ir::ILLds_Store_Id
ir::ILLog_Vec
ir::ILLt
ir::ILMad
ir::ILMov
ir::ILMul
ir::ILNe
ir::ILOperandA class for a basic IL Operand
ir::ILRcp
ir::ILRound_Nearest
ir::ILRound_Neginf
ir::ILRsq_Vec
ir::ILSin_Vec
ir::ILSqrt_Vec
ir::ILStatement
ir::ILSub
ir::ILTrinaryInstructionA generic 3 operand instruction
ir::ILUav_Arena_Load_Id
ir::ILUav_Arena_Store_Id
ir::ILUav_Raw_Load_Id
ir::ILUav_Raw_Store_Id
ir::ILUav_Read_Add_Id
ir::ILUav_Read_Max_Id
ir::ILUav_Read_Min_Id
ir::ILUav_Read_Xchg_Id
ir::ILUdiv
ir::ILUmul
ir::ILUmul24
ir::ILUnaryInstructionA generic 1 operand instruction
ir::ILUshr
ir::ILUtoF
ir::ILWhileLoop
transforms::ImmutableKernelPassAn immutable pass over a single kernel in a module
transforms::ImmutablePassA pass that generates information about a program without modifying it, used to generate data structures
analysis::ControlTree::InstNodeA representation of the cfg basic block
analysis::DataflowGraph::InstructionA class for referring to a generic instruction
ir::InstructionInternal representation of an instruction
int1
int3
trace::InteractiveDebuggerA heavy-weight tool for debugging the emulator
cuda::CudaDriver::InterfaceContainer for pointers to the actual functions
analysis::ControlTree::InvalidNodeInvalid node
transforms::IPDOMReconvergencePassA pass to construct an instruction vector with reconverge points
ir::IRKernel
analysis::ProgramStructureGraph::Block::iteratorAn iterator over the instructions in the contained basic blocks
itimerspec
ir::Kernel
analysis::KernelAnalysisAn analysis over a single kernel
transforms::KernelAndId
executive::LLVMModuleManager::KernelAndTranslation
transforms::KernelDrawerPass
util::KernelExtractorDriver
util::ExtractedDeviceState::KernelLaunch
cuda::KernelLaunchConfiguration
transforms::KernelPassA pass over a single kernel in a module
util::KernelTestHarness
cuda::CudaWorkerThread::LaunchA description of a kernel launch
ldiv_t
transforms::LinearScanRegisterAllocationPassImplements the linear scan register allocation algorithm
lldiv_t
ir::LLVMAddThe LLVM add instruction
ir::LLVMAllocaThe LLVM alloca instruction
ir::LLVMAndThe LLVM And instruction
ir::LLVMAshrThe LLVM ashr instruction
ir::LLVMBinaryInstructionA generic 2 operand instruction
ir::LLVMBitcastThe LLVM bitcast instruction
ir::LLVMBrThe LLVM br instruction
ir::LLVMCallThe LLVM call instruction
ir::LLVMComparisonInstructionA generic comparison instruction
executive::LLVMContextA class contains the state for executing a kernel
ir::LLVMConversionInstructionA generic conversion instruction
executive::LLVMCooperativeThreadArrayA class for managing a CTA executed via LLVM translation
executive::LLVMExecutableKernelExecutes an LLVMKernel using the LLVM JIT
executive::LLVMExecutionManagerControls the execution of worker threads
ir::LLVMExtractelementThe LLVM extractelement instruction
ir::LLVMExtractvalueThe LLVM extractvalue instruction
ir::LLVMFaddThe LLVM fadd instruction
ir::LLVMFcmpThe LLVM fcmp instruction
ir::LLVMFdivThe LLVM fdiv instruction
ir::LLVMFmulThe LLVM fmul instruction
ir::LLVMFpextThe LLVM fpext instruction
ir::LLVMFptosiThe LLVM fptosi instruction
ir::LLVMFptouiThe LLVM fptoui instruction
ir::LLVMFptruncThe LLVM fptrunc instruction
ir::LLVMFreeThe LLVM free instruction
ir::LLVMFremThe LLVM frem instruction
ir::LLVMFsubThe LLVM fsub instruction
executive::LLVMFunctionCallStackA class for managing a call stack for a single PTX thread
ir::LLVMGetelementptrThe LLVM getelementptr instruction
ir::LLVMIcmpThe LLVM icmp instruction
ir::LLVMInsertelementThe LLVM insertelement instruction
ir::LLVMInsertvalueThe LLVM insertvalue instruction
ir::LLVMInstructionA class used to represent any LLVM Instruction
ir::LLVMInttoptrThe LLVM intotoptr instruction
ir::LLVMInvokeThe LLVM invoke instruction
ir::LLVMKernelA class containing a complete representation of an LLVM kernel
ir::LLVMLoadThe LLVM load instruction
ir::LLVMLshrThe LLVM lshr instruction
ir::LLVMMallocThe LLVM malloc instruction
executive::LLVMModuleManagerA class that manages modules that are executed by LLVM kernels
ir::LLVMMulThe LLVM mul instruction
ir::LLVMOrThe LLVM or instruction
ir::LLVMPhiThe LLVM phi instruction
ir::LLVMPtrtointThe LLVM ptrtoint instruction
ir::LLVMRetThe LLVM Add instruction
ir::LLVMSdivThe LLVM sdiv instruction
ir::LLVMSelectThe LLVM select instruction
ir::LLVMSextThe LLVM sext instruction
ir::LLVMShlThe LLVM shl instruction
ir::LLVMShufflevectorThe LLVM shufflevector instruction
ir::LLVMSitofpThe LLVM sitofp instruction
ir::LLVMSremThe LLVM srem instruction
executive::LLVMStateA class for managing global llvm state
ir::LLVMStatementA class for LLVM declarations
ir::LLVMStoreThe LLVM store instruction
ir::LLVMSubThe LLVM sub instruction
ir::LLVMSwitchThe LLVM switch instruction
ir::LLVMTruncThe LLVM trunc instruction
ir::LLVMUdivThe LLVM udiv instruction
ir::LLVMUitofpThe LLVM uitofp instruction
ir::LLVMUnaryInstructionA generic 1 operand instruction
ir::LLVMUnreachableThe LLVM unreachable instruction
ir::LLVMUnwindThe LLVM unwind instruction
ir::LLVMUremThe LLVM urem instruction
ir::LLVMVaArgThe LLVM va_arg instruction
executive::LLVMWorkerThreadA thread responsible for executing CTAs
ir::LLVMXorThe LLVM xor instruction
ir::LLVMZextThe LLVM zext instruction
ir::LocalA class to represent a variable with local scope
long1
long3
longlong1
longlong3
util::ExtractedDeviceState::MemoryAllocation
executive::EmulatorDevice::MemoryAllocationAn interface to a managed memory allocation
executive::Device::MemoryAllocationAn interface to a memory allocation
executive::ATIGPUDevice::MemoryAllocationATI memory allocation
executive::NVIDIAGPUDevice::MemoryAllocationAn interface to a memory allocation on the cuda driver
executive::RemoteDevice::MemoryAllocationAn interface to a managed memory allocation
api::OcelotConfiguration::TraceGeneration::MemoryCheckerCheck memory errors
trace::MemoryCheckerA trace generator for checking all memory accesses
trace::MemoryRaceDetectorA trace generator for checking memory races
executive::LLVMModuleManager::KernelAndTranslation::MetaData
transforms::MIMDThreadSchedulingPassA class for changing the scheduling order of threads assuming execution on a SIMT IPDOM machine
executive::LLVMModuleManager::Module
util::ExtractedDeviceState::Module
ir::Module
executive::EmulatorDevice::ModuleA class for holding the state associated with a module
analysis::ModuleAnalysisAn analysis over a complete module
executive::LLVMModuleManager::ModuleDatabaseA thread safe-class for actually maintaining the modules
transforms::ModulePassA pass over an entire module
executive::MulticoreCPUDeviceA device to control all of the cores in a single CPU
analysis::ControlTree::NaturalNode
ir::LLVMSwitch::NodeClass for a combination of an operand and a label
analysis::ControlTree::NodeA polymorphic base class that represents any node
analysis::StructuralAnalysis::Node
ir::LLVMPhi::NodeClass for a combination of an operand and a label
transforms::AssignFallThroughEdge::NodeCFG
analysis::DataflowGraph::NoProducerExceptionAn exception for potentially uninitialized regs
executive::NVIDIAExecutableKernel
executive::NVIDIAGPUDevice
util::OcelotConfigA class for determining the linker flags required to link against ocelot
api::OcelotConfigurationConfiguration object structure for GPU Ocelot
ocelot::OcelotRuntimeThis is an interface for managing state associated with Ocelot
remote::OcelotServer
remote::OcelotServerConnection
executive::EmulatorDevice::OpenGLResourceA graphics resource with an opengl buffer and pointer
ir::LLVMInstruction::OperandA class for a basic LLVM Operand
parser::PTXParser::State::OperandWrapper
api::OcelotConfiguration::Optimizations
ir::Parameter
ir::LLVMInstruction::ParameterA parameter operand
parser::ParserAn interface that parses a text or binary file and generates an internal representation of a program
transforms::PassA class modeled after the LLVM notion of an optimization pass. Allows different transformations to be applied to PTX modules
transforms::PassManagerA class to orchestrate the execution of many passes
executive::PassThroughDevice
analysis::DataflowGraph::PhiInstructionA class for referring to a phi instruction
analysis::PostdominatorTree
analysis::ProgramStructureGraph::Block::predecessor_iteratorAn iterator over block predecessors
analysis::ProgramStructureGraphProgramStructureGraphs are overlays over the ControlFlowGraph that capture some structure other than basic blocks
executive::Device::PropertiesProperties of a specific device
executive::Device::PropertiesData
ir::PTXKernel::PrototypeDefines a prototype for each kernel and function
pthread_attr_t
pthread_barrier_t
pthread_barrierattr_t
pthread_cond_t
pthread_condattr_t
pthread_mutex_t
pthread_mutexattr_t
pthread_rwlock_t
pthread_rwlockattr_t
PTXChecker
ir::PTXInstruction
ir::PTXKernel
parser::PTXLexerA wrapper around yyFlexLexer to allow for a local variable
ir::PTXOperand
tools::PTXOptimizerAble to run various optimization passes over PTX modules
parser::PTXParserAn implementation of the Parser interface for PTX
ir::PTXStatement
PtxToIlTranslatorA class used to transform a PTX file into an IL equivalent
translator::PTXToILTranslatorA translator from PTX to IL
translator::PTXToLLVMTranslatorA translator from PTX to LLVM
api::OcelotConfiguration::TraceGeneration::RaceDetectorConfiguration properties for trace::RaceDetector
random_data
executive::ReconvergenceBarrier
executive::ReconvergenceIPDOM
executive::ReconvergenceMechanismBase class for abstract reconvergence mechanism within emulator
executive::ReconvergenceTFGen6
executive::ReconvergenceTFSortedStack
trace::ReconvergenceTraceEventTrace events concerned specifically with thread divergence and reconvergence
analysis::DataflowGraph::RegisterA register with type info
analysis::DataflowGraph::Register_Hash
cuda::RegisteredGlobal
cuda::RegisteredKernelReferences a kernel registered to CUDA runtime
cuda::RegisteredTexture
analysis::DataflowGraph::RegisterPointerA register with type info
executive::RemoteDevice
remote::RemoteDeviceMessageA message type for communicating with remote devices
transforms::RemoveBarrierPassA class for a pass that removes all barriers from a PTX kernel
executive::RuntimeException
trace::MemoryChecker::ShadowMemory
short1
short3
transforms::SimplifyExternalCallsPassRemoves parameters passed to external calls to eliminate explicit stack modifications in PTX. The register are passed directly to external calls
transforms::SplitBasicBlockPassA class for splitting basic blocks larger than a specified size
analysis::SSAGraphSSA Graph, used as a helper by the dataflow graph to convert into SSA form
parser::PTXParser::State
ir::PTXStatement::StaticArray
analysis::StructuralAnalysis
transforms::StructuralTransformStructuralTransform - This class holds all the methods and data structures
transforms::SubkernelFormationPassSplit all kernels in a module into sub-kernels. The sub-kernels should be called as functions from the main kernel. The assumption is that all threads will execute a sub-kernel, hit a barrier, and enter the next sub-kernel
analysis::ProgramStructureGraph::Block::successor_iteratorAn iterator over block successors
analysis::SuperblockAnalysisImplements superblock analysis as described in [1]
surface< T, dim >
surface< void, dim >
surfaceReference
ir::PTXStatement::Symbol
transforms::SyncEliminationPassThis pass converts ordinary bra instructions into bra.uni, whenever the divergence analysis deems it safe to do so
test::TestDataflowGraphA test for the DataflowGraph class
test::TestDeviceSwitchingA unit test for the ability of the CUDA runtime to switch between devices and use multiple threads
test::TestDominatorTree
test::TestEmulator
test::TestExternalFunctionsA unit test for calling an external host function from PTX
test::TestPTXAssembly::TestHandleA class for representing a single test
test::TestInstructions
test::TestKernels
test::TestLexerTests for the PTX lexer
test::TestLLVMInstructionsA test for the assembly code generation and automatic verfication of individual LLVM instructions
test::TestLLVMKernelsA unit test for the LLVM executive runtime
test::TestParserA test for the PTXParser class
test::TestPTXAssemblyThe idea here is to define a test harness for a large number of PTX unit tests
test::TestPTXToLLVMTranslatorThis is a basic test that just tries to get through a translation successfully of as many PTX programs as possible
ir::TextureA class to represent the access format of a texture
texture< T, texType, mode >
textureReference
test::Thread
analysis::ThreadFrontierAnalysisA class for determining thread frontiers for all basic blocks
transforms::ThreadFrontierReconvergencePassA pass to construct an instruction vector with reconverge points at thread frontiers
timespec
timeval
tm
test::ToId
trace::TokenCommand token
trace::TraceEvent
cuda::TraceGeneratingCudaRuntimeThe main high performance implementation of the CUDA API
api::OcelotConfiguration::TraceGenerationConfiguration for trace generation facilities
trace::TraceGenerator
translator::TranslatorAn interface for a translator from one ISA to another
ir::LLVMInstruction::TypeA class for an LLVM basic or derived type
uchar1
uchar3
uint1
uint3
ulong1
ulong3
ulonglong1
ulonglong3
ushort1
ushort3
ir::LLVMInstruction::ValueThe value of the operand if it is a constant
ir::Parameter::ValueType
wait
trace::InteractiveDebugger::WatchpointWatchpoint datastructure
analysis::ControlTree::WhileNode
executive::WorkerMessage
cuda::WorkerMessage
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